A communication interface enables data transmission between two or more electronic devices including host and peripheral devices. For example, mobile industry processor interface (MIPI) is widely adopted communication interface standard between a host device and a peripheral device, and is prevalent in products such as mobile electronic devices, digital cameras, display devices, modems, RFIC (radio frequency integrated circuit), and portable tablets and laptop computers. MIPI is standardized interconnect protocol between a host and peripherals and is based on very high-speed serial interface, optimized for power. There are several higher layer standards in MIPI such as a display serial interface (DSI), a camera serial interface (CSI), an interface between radio frequency transceiver integrated circuit and baseband integrated circuit (DigRF) and low latency interface (LLI), and so forth along with physical layer specifications such as D-PHY and M-PHY.
D-PHY specification provides a high-speed serial interface solution for communications between various components in an electronic device. The D-PHY solution is capable of expanding a bandwidth of a transmission interface through a low-power consumption approach. For data transmission, the MIPI D-PHY specification defines two modes—a high-speed mode (<1 Gbps) and a low-power mode (<10 Mbps). The high-speed mode is used for high-speed data traffic and low power mode is used for transferring control information. In high-speed mode, there is a source synchronous clock on a separate lane between the host and peripherals. In contrast, the low power mode is achieved through a bidirectional data lane between the host and peripherals and the clock is expected to be extracted from the bidirectional data lane. Moreover, low power clock frequency of the host is to be manually adjusted within a certain range (typically, 67% to 150%) of low power clock frequency of peripheral connected to the host based on the knowledge of peripheral low power clock frequency published or specified by manufacturer of the peripheral.
However, any variations between peripheral's published low power clock frequency and actual low power clock frequency due to components tolerances may lead to low power link failure between host and peripheral. Similarly, any variations in adjusted host low power clock frequency due to clock adjustment circuitry precision may lead to low power link failure between host and peripheral if adjusted host clock frequency crosses the allowed range around actual low power clock frequency of peripheral. The low power link failure between host and peripheral is catastrophic, as the peripheral will become unusable. Moreover, the static adjustment of the host low power clock frequency for a given peripheral or a set of peripheral may not be suitable for another peripheral.